Datasheet

Section 15 Serial Communication Interface (SCI, IrDA)

Rev. 4.00 Sep 27, 2006 page 490 of 1130

REJ09B0327-0400

Restrictions on Use of DTC

• When an external clock source is used as the serial clock, the transmit clock should not be

input until at least 5 φ clock cycles after TDR is updated by the DTC. Misoperation may occur

if the transmit clock is input within 4 clock cycles after TDR is updated. (Figure 15.24)

• When RDR is read by the DTC, be sure to set the activation source to the relevant SCI receive-

data-full interrupt (RXI).

LSB

Serial data

SCK

D3 D4 D5D2 D6 D7

Note: When operating on an external clock, set t > 4 states.

TDRE

Figure 15.24 Example of Synchronous Transmission by DTC