Datasheet

Section 15 Serial Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 484 of 1130
REJ09B0327-0400
The high-level pulse width is fixed at a minimum of 1.41 µs, and a maximum of (3/16 + 2.5%) ×
bit rate or (3/16 × bit rate) + 1.08 µs. When system clock φ is 20 MHz, 1.6 µs can be set as the
minimum high-level pulse width at 1.41 µs or above.
When the serial data is 1, no pulse is output.
0000 0
UART frame
IR frame
Data
Data
Start
bit
Stop
bit
Start
bit
Stop
bit
11 111
0000 011 111
Pulse width is 1.6 µs
to 3/16 bit interval
Transmission
Reception
Bit
interval
Figure 15.22 IrDA Transmit/Receive Operations
Reception
In reception, IR frame data is converted to a UART frame by the IrDA interface, and input to the
SCI.
When a high-level pulse is detected, 0 data is output, and if there is no pulse during a one-bit
interval, 1 data is output. Note that a pulse shorter than the minimum pulse width of 1.41 µs will
be identified as a 0 signal.