Datasheet

Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 3 of 1130
REJ09B0327-0400
Item Specifications
Bus controller
• 2-state or 3-state access space can be designated for external
expansion areas
• Number of program wait states can be set for external expansion areas
Data transfer
controller (DTC)
(H8S/2148 Group)
• Can be activated by internal interrupt or software
• Multiple transfers or multiple types of transfer possible for one
activation source
• Transfer possible in repeat mode, block transfer mode, etc.
• Request can be sent to CPU for interrupt that activated DTC
16-bit free-running
timer module
(FRT: 1 channel)
• One 16-bit free-running counter (also usable for external event
counting)
• Two output compare outputs
• Four input capture inputs (with buffer operation capability)
8-bit timer module
(2 channels: TMR0,
TMR1)
Each channel has:
• One 8-bit up-counter (also usable for external event counting)
• Two timer constant registers
• The two channels can be connected
Timer connection and
8-bit timer module
(TMR) (2 channels:
TMRX, TMRY)
(Timer connection and
TMRX provided in
H8S/2148 Group)
Input/output and FRT, TMR1, TMRX, TMRY can be interconnected
• Measurement of input signal or frequency-divided waveform pulse
width and cycle (FRT, TMR1)
• Output of waveform obtained by modification of input signal edge (FRT,
TMR1)
• Determination of input signal duty cycle (TMRX)
• Output of waveform synchronized with input signal (FRT, TMRX,
TMRY)
• Automatic generation of cyclical waveform (FRT, TMRY)
Watchdog timer
module
(WDT: 2 channels)
• Watchdog timer or interval timer function selectable
• Subclock operation capability (channel 1 only)
8-bit PWM timer
(PWM)
(H8S/2148 Group and
H8S/2147N)
• Up to 16 outputs
• Pulse duty cycle settable from 0 to 100%
• Resolution: 1/256
• 1.25 MHz maximum carrier frequency (20-MHz operation)