Datasheet

Section 15 Serial Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 436 of 1130
REJ09B0327-0400
external clock operation (CKE1 = 1). The setting of bits CKE1 and CKE0 must be carried out
before the SCI’s operating mode is determined using SMR.
For details of clock source selection, see table 15.9 in section 15.3, Operation.
Bit 1 Bit 0
CKE1 CKE0 Description
0 0 Asynchronous mode Internal clock/SCK pin functions as I/O port
*
1
Synchronous mode Internal clock/SCK pin functions as serial clock
output
*
1
1 Asynchronous mode Internal clock/SCK pin functions as clock output
*
2
Synchronous mode Internal clock/SCK pin functions as serial clock
output
1 0 Asynchronous mode External clock/SCK pin functions as clock input
*
3
Synchronous mode External clock/SCK pin functions as serial clock
input
1 Asynchronous mode External clock/SCK pin functions as clock input
*
3
Synchronous mode External clock/SCK pin functions as serial clock
input
Notes: 1. Initial value
2. Outputs a clock of the same frequency as the bit rate.
3. Inputs a clock with a frequency 16 times the bit rate.
15.2.7 Serial Status Register (SSR)
7
TDRE
1
R/(W)
*
6
RDRF
0
R/(W)
*
5
ORER
0
R/(W)
*
4
FER
0
R/(W)
*
3
PER
0
R/(W)
*
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Bit
Initial value
Read/Write
Note: * Only 0 can be written, to clear the flag.
SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and
multiprocessor bits.
SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags
TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be
read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified.