Datasheet

Section 14 Watchdog Timer (WDT)
Rev. 4.00 Sep 27, 2006 page 413 of 1130
REJ09B0327-0400
TCSR0 Bit 4—Reset Select (RSTS): Reserved. This bit should not be set to 1.
TCSR1 Bit 4—Prescaler Select (PSS): Selects the input clock source for TCNT in WDT1. For
details, see the description of the CKS2 to CKS0 bits below.
WDT1 TCSR
Bit 4
PSS Description
0 TCNT counts φ-based prescaler (PSM) divided clock pulses (Initial value)
1 TCNT counts φSUB-based prescaler (PSS) divided clock pulses
Bit 3—Reset or NMI (RST/NMI
NMINMI
NMI): Specifies whether an internal reset or NMI interrupt is
requested on TCNT overflow in watchdog timer mode.
Bit 3
RST/NMI
NMINMI
NMI Description
0 An NMI interrupt is requested (Initial value)
1 An internal reset is requested
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select an internal clock source,
obtained by dividing the system clock (φ), or subclock (φSUB) for input to TCNT.
• WDT0 input clock selection
Bit 2 Bit 1 Bit 0 Description
CKS2 CKS1 CKS0 Clock Overflow Period
*
(when φ
φφ
φ = 20 MHz)
000 φ/2 (Initial value) 25.6 µs
1 φ/64 819.2 µs
10 φ/128 1.6 ms
1 φ/512 6.6 ms
100 φ/2048 26.2 ms
1 φ/8192 104.9 ms
10 φ/32768 419.4 ms
1 φ/131072 1.68 s
Note: * The overflow period is the time from when TCNT starts counting up from H'00 until
overflow occurs.