Datasheet

Section 14 Watchdog Timer (WDT)
Rev. 4.00 Sep 27, 2006 page 409 of 1130
REJ09B0327-0400
Overflow
TCNT TCSR
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Clock
Clock
select
Interrupt
control
Reset
control
Internal clock
source
Bus
interface
Module bus
Internal bus
WDT1
WOVI1
(interrupt request
signal)
Internal reset
signal
*
1
Internal NMI
(interrupt request
signal)
*
2
Legend:
TCSR: Timer control/status register
TCNT: Timer counter
φ
SUB
/2
φ
SUB
/4
φ
SUB
/8
φ
SUB
/16
φ
SUB
/32
φ
SUB
/64
φ
SUB
/128
φ
SUB
/256
RESO signal
*
1
Notes: 1. RESO pin output goes low when the internal reset signal is generated by overflow of TCNT
in either WDT0 or WDT1. The reset of the WDT that overflowed first takes precedence over
the internal reset signal.
2. The internal NMI interrupt request signal can be output independently by either WDT0 or
WDT1. The interrupt controller does not distinguish between NMI interrupt requests from
WDT0 and WDT1.
Figure 14.1 (b) Block Diagram of WDT1
14.1.3 Pin Configuration
Table 14.1 describes the WDT input pin.
Table 14.1 WDT Pin
Name Symbol I/O Function
Reset output pin RESO Output Watchdog timer mode counter overflow signal
output
External subclock input pin EXCL Input WDT1 prescaler counter input clock