Datasheet

Rev. 4.00 Sep 27, 2006 page xliii of xliv
26.7.5 Timing of On-Chip Supporting Modules............................................................. 919
Appendix A Instruction Set .............................................................................................. 925
A.1 Instruction......................................................................................................................... 925
A.2 Instruction Codes .............................................................................................................. 943
A.3 Operation Code Map......................................................................................................... 957
A.4 Number of States Required for Execution ........................................................................ 961
A.5 Bus States during Instruction Execution........................................................................... 974
Appendix B Internal I/O Registers................................................................................. 990
B.1 Addresses.......................................................................................................................... 990
B.2 Register Selection Conditions........................................................................................... 997
B.3 Functions......................................................................................................................... 1004
Appendix C I/O Port Block Diagrams......................................................................... 1086
C.1 Port 1 Block Diagram ..................................................................................................... 1086
C.2 Port 2 Block Diagrams.................................................................................................... 1087
C.3 Port 3 Block Diagram ..................................................................................................... 1090
C.4 Port 4 Block Diagrams.................................................................................................... 1091
C.5 Port 5 Block Diagrams.................................................................................................... 1098
C.6 Port 6 Block Diagrams.................................................................................................... 1101
C.7 Port 7 Block Diagrams.................................................................................................... 1106
C.8 Port 8 Block Diagrams.................................................................................................... 1107
C.9 Port 9 Block Diagrams.................................................................................................... 1113
C.10 Port A Block Diagrams................................................................................................... 1118
C.11 Port B Block Diagram..................................................................................................... 1121
Appendix D Pin States..................................................................................................... 1124
D.1 Port States in Each Processing State............................................................................... 1124
Appendix E Timing of Transition to and Recovery from Hardware
Standby Mode ............................................................................................ 1126
E.1 Timing of Transition to Hardware Standby Mode .......................................................... 1126
E.2 Timing of Recovery from Hardware Standby Mode....................................................... 1126
Appendix F Product Code Lineup................................................................................ 1127
Appendix G Package Dimensions ................................................................................ 1129