Datasheet

Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 392 of 1130
REJ09B0327-0400
Table 13.3 Examples of TCR Settings
Bit(s) Abbreviation Contents Description
7
6
5
CMIEB
CMIEA
OVIE
0
0
0
Interrupts due to compare-match and overflow are
disabled
4 and 3 CCLR1, CCLR0 11 TCNT is cleared by the rising edge of the external
reset signal (IHI signal)
2 to 0 CKS2 to CKS0 001 Incremented on internal clock: φ
Table 13.4 Examples of TCORB (Pulse Width Threshold) Settings
φ
φφ
φ:10 MHz φ
φφ
φ: 12 MHz φ
φφ
φ: 16 MHz φ
φφ
φ: 20 MHz
H'07 0.8 µs 0.67 µs 0.5 µs 0.4 µs
H'0F 1.6 µs 1.33 µs 1 µs 0.8 µs
H'1F 3.2 µs 2.67 µs 2 µs 1.6 µs
H'3F 6.4 µs 5.33 µs 4 µs 3.2 µs
H'7F 12.8 µs 10.67 µs 8 µs 6.4 µs
IHI signal
Counter reset
caused by
IHI signal
Counter clear
caused by
TCNT overflow
At the 2nd compare-match,
IHI signal is not tested
IHI signal is tested
at compare-match
PDC signal
TCNT
TCORB
(threshold)
Figure 13.2 Timing Chart for PWM Decoding