Datasheet

Section 13 Timer Connection
Rev. 4.00 Sep 27, 2006 page 389 of 1130
REJ09B0327-0400
Bit 3—VFBACKI Edge (VFEDG): Detects a rising edge on the VFBACKI pin.
Bit 3
VFEDG Description
0 [Clearing condition]
When 0 is written in VFEDG after reading VFEDG = 1
(Initial value)
1 [Setting condition]
When a rising edge is detected on the VFBACKI pin
Bit 2—Pre-Equalization Flag (PREQF): Detects the occurrence of an IHI signal 2fH
modification condition. The generation of a falling/rising edge in the IHI signal during a mask
interval is expressed as the occurrence of a 2fH modification condition. For details, see section
13.3.4, IHI Signal 2fH Modification.
Bit 2
PREQF Description
0 [Clearing condition]
When 0 is written in PREQF after reading PREQF = 1
(Initial value)
1 [Setting condition]
When an IHI signal 2fH modification condition is detected
Bit 1—IHI Signal Level (IHI): Indicates the current level of the IHI signal. Signal source and
phase inversion selection for the IHI signal depends on the contents of TCONRI. Read this bit to
determine whether the input signal is positive or negative, then maintain the IHI signal at positive
phase by modifying TCONRI.
Bit 1
IHI Description
0 The IHI signal is low
1 The IHI signal is high