Datasheet

Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 373 of 1130
REJ09B0327-0400
12.6.3 Contention between TCOR Write and Compare-Match
During the T2 state of a TCOR write cycle, the TCOR write has priority even if a compare-match
occurs and the compare-match signal is disabled. Figure 12.15 shows this operation.
With TMRX, an ICR input capture contends with a compare-match in the same way as with a
write to TCORC. In this case, the input capture has priority and the compare-match signal is
inhibited.
φ
Address
TCOR address
Internal write signal
TCNT
TCOR
NM
T
1
T
2
TCOR write cycle by CPU
TCOR write data
NN + 1
Compare-match signal
Inhibited
Figure 12.15 Contention between TCOR Write and Compare-Match