Datasheet

Section 12 8-Bit Timers
Rev. 4.00 Sep 27, 2006 page 371 of 1130
REJ09B0327-0400
12.6 Usage Notes
Application programmers should note that the following kinds of contention can occur in the 8-bit
timer module.
12.6.1 Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear
takes priority, so that the counter is cleared and the write is not performed. Figure 12.13 shows
this operation.
φ
Address
TCNT address
Internal write signal
Counter clear signal
TCNT
N H'00
T
1
T
2
TCNT write cycle by CPU
Figure 12.13 Contention between TCNT Write and Clear