Datasheet

Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 336 of 1130
REJ09B0327-0400
Contention between FRC Write and Increment
If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes
priority and FRC is not incremented.
Figure 11.19 shows this type of contention.
T
1
T
2
FRC write cycle
Address
Internal write signal
φ
FRC input clock
FRC N M
Write data
FRC address
Figure 11.19 FRC Write-Increment Contention
Contention between OCR Write and Compare-Match
If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes
priority and the compare-match signal is inhibited.
Figure 11.20 shows this type of contention.