Datasheet

Rev. 4.00 Sep 27, 2006 page xxxv of xliv
15.3 Operation .......................................................................................................................... 453
15.3.1 Overview.............................................................................................................. 453
15.3.2 Operation in Asynchronous Mode....................................................................... 455
15.3.3 Multiprocessor Communication Function............................................................ 466
15.3.4 Operation in Synchronous Mode ......................................................................... 474
15.3.5 IrDA Operation.................................................................................................... 483
15.4 SCI Interrupts.................................................................................................................... 486
15.5 Usage Notes ...................................................................................................................... 487
Section 16 I
2
C Bus Interface [Option]........................................................................... 491
16.1 Overview........................................................................................................................... 491
16.1.1 Features................................................................................................................ 491
16.1.2 Block Diagram..................................................................................................... 492
16.1.3 Input/Output Pins................................................................................................. 494
16.1.4 Register Configuration......................................................................................... 495
16.2 Register Descriptions........................................................................................................ 496
16.2.1 I
2
C Bus Data Register (ICDR) ............................................................................. 496
16.2.2 Slave Address Register (SAR)............................................................................. 499
16.2.3 Second Slave Address Register (SARX) ............................................................. 500
16.2.4 I
2
C Bus Mode Register (ICMR)........................................................................... 501
16.2.5 I
2
C Bus Control Register (ICCR)......................................................................... 504
16.2.6 I
2
C Bus Status Register (ICSR)............................................................................ 511
16.2.7 Serial/Timer Control Register (STCR) ................................................................ 516
16.2.8 DDC Switch Register (DDCSWR)...................................................................... 518
16.2.9 Module Stop Control Register (MSTPCR).......................................................... 520
16.3 Operation .......................................................................................................................... 521
16.3.1 I
2
C Bus Data Format ............................................................................................ 521
16.3.2 Master Transmit Operation.................................................................................. 523
16.3.3 Master Receive Operation.................................................................................... 525
16.3.4 Slave Receive Operation...................................................................................... 528
16.3.5 Slave Transmit Operation .................................................................................... 531
16.3.6 IRIC Setting Timing and SCL Control ................................................................ 533
16.3.7 Automatic Switching from Formatless Mode to I
2
C Bus Format ........................ 534
16.3.8 Operation Using the DTC .................................................................................... 535
16.3.9 Noise Canceler..................................................................................................... 536
16.3.10 Sample Flowcharts............................................................................................... 536
16.3.11 Initialization of Internal State .............................................................................. 541
16.4 Usage Notes ...................................................................................................................... 542
Section 17 Keyboard Buffer Controller........................................................................ 559
17.1 Overview........................................................................................................................... 559