Datasheet

Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 321 of 1130
REJ09B0327-0400
Bit 2—Buffer Enable B (BUFEB): Selects whether ICRD is to be used as a buffer register for
ICRB.
Bit 2
BUFEB Description
0 ICRD is not used as a buffer register for input capture B (Initial value)
1 ICRD is used as a buffer register for input capture B
Bits 1 and 0—Clock Select (CKS1, CKS0): Select external clock input or one of three internal
clock sources for the FRC. External clock pulses are counted on the rising edge of signals input to
the external clock input pin (FTCI).
Bit 1 Bit 0
CKS1 CKS0 Description
00 φ/2 internal clock source (Initial value)
1 φ/8 internal clock source
10 φ/32 internal clock source
1 External clock source (rising edge)
11.2.9 Timer Output Compare Control Register (TOCR)
Bit
Initial value
Read/Write
7
ICRDMS
0
R/W
6
OCRAMS
0
R/W
5
ICRS
0
R/W
4
OCRS
0
3
OEA
0
0
OLVLB
0
R/W
2
OEB
0
R/W
1
OLVLA
0
R/W
R/W
R/W
TOCR is an 8-bit readable/writable register that enables output from the output compare pins,
selects the output levels, switches access between output compare registers A and B, controls the
ICRD and OCRA operating mode, and switches access to input capture registers A, B, and C.
TOCR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Input Capture D Mode Select (ICRDMS): Specifies whether ICRD is used in the normal
operating mode or in the operating mode using OCRDM.