Datasheet

Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 319 of 1130
REJ09B0327-0400
Bit 1—Timer Overflow Flag (OVF): This status flag indicates that the FRC has overflowed
(changed from H'FFFF to H'0000). This flag must be cleared by software. It is set by hardware,
however, and cannot be set by software.
Bit 1
OVF Description
0 [Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
(Initial value)
1 [Setting condition]
When FRC changes from H'FFFF to H'0000
Bit 0—Counter Clear A (CCLRA): This bit selects whether the FRC is to be cleared at compare-
match A (when the FRC and OCRA values match).
Bit 0
CCLRA Description
0 FRC clearing is disabled (Initial value)
1 FRC is cleared at compare-match A
11.2.8 Timer Control Register (TCR)
Bit
Initial value
Read/Write
7
IEDGA
0
R/W
6
IEDGB
0
R/W
5
IEDGC
0
R/W
4
IEDGD
0
R/W
3
BUFEA
0
R/W
0
CKS0
0
R/W
2
BUFEB
0
R/W
1
CKS1
0
R/W
TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input capture
signals, enables the input capture buffer mode, and selects the FRC clock source.
TCR is initialized to H'00 by a reset and in hardware standby mode
Bit 7—Input Edge Select A (IEDGA): Selects the rising or falling edge of the input capture A
signal (FTIA).