Datasheet

Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 308 of 1130
REJ09B0327-0400
11.1.2 Block Diagram
Figure 11.1 shows a block diagram of the free-running timer.
External
clock source
Internal
clock sources
Clock select
Comparator A
OCRA (H/L)
Comparator B
OCRB (H/L)
Bus interface
Internal
data bus
φ/2
φ/8
φ/32
FTCI
Compare-
match A
Clear
Clock
FTOA
FTOB
Overflow
ICRA (H/L)
Compare-
match B
Input capture
FRC (H/L)
TCSR
FTIA
FTIB
FTIC
FTID
Control
logic
Module data bus
TIER
TCR
TOCR
Interrupt signals
ICIA
ICIB
ICIC
ICID
OCIA
OCIB
FOVI
Legend:
OCRA, B:
FRC:
ICRA, B, C, D:
TCSR:
Output compare register A, B (16 bits)
Free-running counter (16 bits)
Input capture register A, B, C, D (16 bits)
Timer control/status register (8 bits)
TIER:
TCR:
TOCR:
Timer interrupt enable register (8 bits)
Timer control register (8 bits)
Timer output compare control
register (8 bits)
ICRB (H/L)
ICRC (H/L)
ICRD (H/L)
OCRA R/F (H/L)
+
+
OCRDM L
×1
×2
Comparator M
Compare-match M
Figure 11.1 Block Diagram of 16-Bit Free-Running Timer