Datasheet

Section 10 14-Bit PWM Timer (PWMX)
Rev. 4.00 Sep 27, 2006 page 303 of 1130
REJ09B0327-0400
Table 10.4 Settings and Operation (Examples when φ
φφ
φ = 10 MHz)
Fixed DADR Bits
Bit Data
CKS
Resolution
T
(µs)
CFS
Base
Cycle
(µs)
Conversion
Cycle
(µs)
T
L
(if OS = 0)
T
H
(if OS = 1)
Precision
(Bits)
3210
Conversion
Cycle
*
(µs)
1. Always low (or high)
level output
(DADR = H'0001 to
H'03FD)
14 1638.4
12 0 0 409.6
0 6.4 1638.4
2. (Data value) × T
(DADR = H'0401 to
H'FFFD)
10 0 0 0 0 102.4
1. Always low (or high)
level output
(DADR = H'0003 to
H'00FF)
14 1638.4
12 0 0 409.6
00.1
1 25.6 1638.4
2. (Data value) × T
(DADR = H'0103 to
H'FFFF)
10 0 0 0 0 102.4
1. Always low (or high)
level output
(DADR = H'0001 to
H'03FD)
14 3276.8
12 0 0 819.2
0 12.8 3276.8
2. (Data value) × T
(DADR = H'0401 to
H'FFFD)
10 0 0 0 0 204.8
1. Always low (or high)
level output
(DADR = H'0003 to
H'00FF)
14 3276.8
12 0 0 819.2
10.2
1 51.2 3276.8
2. (Data value) × T
(DADR = H'0103 to
H'FFFF)
10 0 0 0 0 204.8
Note: * This column indicates the conversion cycle when specific DADR bits are fixed.