Datasheet

Section 9 8-Bit PWM Timers
Rev. 4.00 Sep 27, 2006 page 282 of 1130
REJ09B0327-0400
9.2 Register Descriptions
9.2.1 PWM Register Select (PWSL)
Bit
Initial value
Read/Write
7
PWCKE
0
R/W
6
PWCKS
0
R/W
5
—
1
4
—
0
3
RS3
0
R/W
0
RS0
0
R/W
2
RS2
0
R/W
1
RS1
0
R/W
—
—
PWSL is an 8-bit readable/writable register used to select the PWM timer input clock and the
PWM data register.
PWSL is initialized to H'20 by a reset, and in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bits 7 and 6—PWM Clock Enable, PWM Clock Select (PWCKE, PWCKS): These bits,
together with bits PWCKA and PWCKB in PCSR, select the internal clock input to TCNT in the
PWM timer.
PWSL PCSR
Bit 7 Bit 6 Bit 2 Bit 1
PWCKE PWCKS PWCKB PWCKA Description
0 — — — Clock input is disabled (Initial value)
10 ——φ (system clock) is selected
100φ/2 is selected
1 φ/4 is selected
10φ/8 is selected
1 φ/16 is selected
The PWM resolution, PWM conversion period, and carrier frequency depend on the selected
internal clock, and can be found from the following equations.
Resolution (minimum pulse width) = 1/internal clock frequency
PWM conversion period = resolution × 256
Carrier frequency = 16/PWM conversion period
Thus, with a 20-MHz system clock (φ), the resolution, PWM conversion period, and carrier
frequency are as shown below.