Datasheet

Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 266 of 1130
REJ09B0327-0400
8.11.2 Register Configuration
Table 8.22 summarizes the port A registers.
Table 8.22 Port A Registers
Name Abbreviation R/W Initial Value Address
*
1
Port A data direction register PADDR W H'00 H'FFAB
*
2
Port A output data register PAODR R/W H'00 H'FFAA
Port A input data register PAPIN R Undefined H'FFAB
*
2
Notes: 1. Lower 16 bits of the address.
2. PADDR and PAPIN have the same address.
Port A Data Direction Register (PADDR)
Bit 76543210
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
Initial value00000000
Read/Write W W W W W W W W
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A.
Setting a PADDR bit to 1 makes the corresponding port A pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
PADDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Port A Output Data Register (PAODR)
Bit 76543210
PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR
Initial value00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
PAODR is an 8-bit readable/writable register that stores output data for the port A pins (PA7 to
PA0). PAODR can always be read or written to, regardless of the contents of PADDR.