Datasheet

Rev. 4.00 Sep 27, 2006 page xxviii of xliv
Section 6 Bus Controller ................................................................................................... 151
6.1 Overview........................................................................................................................... 151
6.1.1 Features................................................................................................................ 151
6.1.2 Block Diagram..................................................................................................... 152
6.1.3 Pin Configuration................................................................................................. 153
6.1.4 Register Configuration......................................................................................... 153
6.2 Register Descriptions........................................................................................................ 154
6.2.1 Bus Control Register (BCR) ................................................................................ 154
6.2.2 Wait State Control Register (WSCR) .................................................................. 155
6.3 Overview of Bus Control.................................................................................................. 157
6.3.1 Bus Specifications................................................................................................ 157
6.3.2 Advanced Mode................................................................................................... 158
6.3.3 Normal Mode....................................................................................................... 158
6.3.4 I/O Select Signal .................................................................................................. 159
6.4 Basic Bus Interface ........................................................................................................... 160
6.4.1 Overview.............................................................................................................. 160
6.4.2 Data Size and Data Alignment............................................................................. 160
6.4.3 Valid Strobes........................................................................................................ 162
6.4.4 Basic Timing........................................................................................................ 163
6.4.5 Wait Control ........................................................................................................ 171
6.5 Burst ROM Interface......................................................................................................... 173
6.5.1 Overview.............................................................................................................. 173
6.5.2 Basic Timing........................................................................................................ 173
6.5.3 Wait Control ........................................................................................................ 175
6.6 Idle Cycle.......................................................................................................................... 175
6.6.1 Operation ............................................................................................................. 175
6.6.2 Pin States in Idle Cycle........................................................................................ 176
6.7 Bus Arbitration.................................................................................................................. 177
6.7.1 Overview.............................................................................................................. 177
6.7.2 Operation ............................................................................................................. 177
6.7.3 Bus Transfer Timing............................................................................................ 178
Section 7 Data Transfer Controller (DTC)................................................................... 179
7.1 Overview........................................................................................................................... 179
7.1.1 Features................................................................................................................ 179
7.1.2 Block Diagram..................................................................................................... 180
7.1.3 Register Configuration......................................................................................... 181
7.2 Register Descriptions........................................................................................................ 182
7.2.1 DTC Mode Register A (MRA) ............................................................................ 182
7.2.2 DTC Mode Register B (MRB)............................................................................. 184
7.2.3 DTC Source Address Register (SAR).................................................................. 185