Datasheet

Rev. 4.00 Sep 27, 2006 page xxvii of xliv
Section 5 Interrupt Controller .......................................................................................... 113
5.1 Overview........................................................................................................................... 113
5.1.1 Features................................................................................................................ 113
5.1.2 Block Diagram..................................................................................................... 114
5.1.3 Pin Configuration................................................................................................. 115
5.1.4 Register Configuration......................................................................................... 116
5.2 Register Descriptions........................................................................................................ 117
5.2.1 System Control Register (SYSCR)...................................................................... 117
5.2.2 Interrupt Control Registers A to C (ICRA to ICRC)............................................ 118
5.2.3 IRQ Enable Register (IER) .................................................................................. 119
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 119
5.2.5 IRQ Status Register (ISR).................................................................................... 120
5.2.6 Keyboard Matrix Interrupt Mask Register (KMIMR) ......................................... 122
5.2.7 Keyboard Matrix Interrupt Mask Register (KMIMRA)....................................... 122
5.2.8 Address Break Control Register (ABRKCR)....................................................... 124
5.2.9 Break Address Registers A, B, C (BARA, BARB, BARC)................................. 125
5.3 Interrupt Sources............................................................................................................... 126
5.3.1 External Interrupts ............................................................................................... 126
5.3.2 Internal Interrupts................................................................................................. 128
5.3.3 Interrupt Exception Vector Table ........................................................................ 128
5.4 Address Breaks ................................................................................................................. 132
5.4.1 Features................................................................................................................ 132
5.4.2 Block Diagram..................................................................................................... 132
5.4.3 Operation ............................................................................................................. 133
5.4.4 Usage Notes......................................................................................................... 133
5.5 Interrupt Operation............................................................................................................ 135
5.5.1 Interrupt Control Modes and Interrupt Operation................................................ 135
5.5.2 Interrupt Control Mode 0..................................................................................... 138
5.5.3 Interrupt Control Mode 1..................................................................................... 140
5.5.4 Interrupt Exception Handling Sequence .............................................................. 143
5.5.5 Interrupt Response Times .................................................................................... 145
5.6 Usage Notes ...................................................................................................................... 146
5.6.1 Contention between Interrupt Generation and Disabling..................................... 146
5.6.2 Instructions That Disable Interrupts..................................................................... 147
5.6.3 Interrupts during Execution of EEPMOV Instruction.......................................... 147
5.7 DTC Activation by Interrupt............................................................................................. 148
5.7.1 Overview.............................................................................................................. 148
5.7.2 Block Diagram..................................................................................................... 148
5.7.3 Operation ............................................................................................................. 149