Datasheet

Section 8 I/O Ports
Rev. 4.00 Sep 27, 2006 page 222 of 1130
REJ09B0327-0400
8.2.2 Register Configuration
Table 8.4 shows the port 1 register configuration.
Table 8.4 Port 1 Registers
Name Abbreviation R/W Initial Value Address
*
Port 1 data direction register P1DDR W H'00 H'FFB0
Port 1 data register P1DR R/W H'00 H'FFB2
Port 1 MOS pull-up control
register
P1PCR R/W H'00 H'FFAC
Note: * Lower 16 bits of the address.
Port 1 Data Direction Register (P1DDR)
7
P17DDR
0
W
6
P16DDR
0
W
5
P15DDR
0
W
4
P14DDR
0
W
3
P13DDR
0
W
0
P10DDR
0
W
2
P12DDR
0
W
1
P11DDR
0
W
Bit
Initial value
Read/Write
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 1. P1DDR cannot be read; if it is, an undefined value will be returned.
P1DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode. The address output pins maintain their output state in a transition to
software standby mode.
• Mode 1
The corresponding port 1 pins are address outputs, regardless of the P1DDR setting.
In hardware standby mode, the address outputs go to the high-impedance state.
• Modes 2 and 3 (EXPE = 1)
The corresponding port 1 pins are address outputs or PWM outputs when P1DDR bits are set
to 1, and input ports when cleared to 0.
• Modes 2 and 3 (EXPE = 0)
The corresponding port 1 pins are output ports or PWM outputs when P1DDR bits are set to 1,
and input ports when cleared to 0.