Datasheet
Rev. 4.00 Sep 27, 2006 page xxi of xliv
Item Page Revision (See Manual for Details)
A.1 Instruction
Table A.1 Instruction
Set
930 Table A.1 amended
2. Arithmetic Instructions
Mnemonic
Addressing Mode and
Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
IHNZVC
EXTU
TAS
EXTU.W Rd
EXTU.L ERd
TAS @ERd
*3
0 → (<bits 15 to 8> of Rd16)
0 → (<bits 31 to 16> of ERd32)
@ERd-0 → CCR set, (1) →
(<bit 7> of @ERd)
W
L
B
2
2
1
1
4
Operation
Condition Code
No. of
States
*
1
Normal
Advanced
Size
4
——— 00
——— 00
——— 0
933 Table A.1 amended
4. Shift Instructions
Mnemonic
Addressing Mode and
Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
IHNZVC
SHLR SHLR.B Rd
SHLR.B #2,Rd
SHLR.W Rd
SHLR.W #2,Rd
SHLR.L ERd
SHLR.L #2,ERd
B
B
W
W
L
L
2
2
2
2
2
2
—
—
—
—
—
—
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
Operation
Condition Code
No. of
States
*
1
Normal
Advanced
Size
0
C
MSB
LSB
939 Table A.1 amended
6. Branch Instructions
Mnemonic
Addressing Mode and
Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
IHNZVC
JMP
BSR
JSR
RTS
JMP @ERn
JMP @aa:24
JMP @@aa:8
BSR d:8
BSR d:16
JSR @ERn
JSR @aa:24
JSR @@aa:8
RTS
PC←ERn
PC←aa:24
PC←@aa:8
PC→@-SP,PC←PC+d:8
PC→@-SP,PC←PC+d:16
PC→@-SP,PC←ERn
PC→@-SP,PC←aa:24
PC→@-SP,PC←@aa:8
PC←@SP+
—
—
—
—
—
—
—
—
—
2
2
4
4
—
—
—
—
—
—
—
—
—
2
3
2
4
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Operation
Condition Code
No. of
States
*
1
Normal
Advanced
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Size
4
3
4
3
4
4
4
5
4
5
4
5
6
5
A.2 Instruction Codes
Table A.2 Instruction
Codes
949 Table A.2 amended
LDC @aa:16,CCR
LDC @aa:16,EXR
Mnemonic
Size
Instruction Format
1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte
Instruc-
tion
LDC
W
W
0
0
1
1
4
4
0
1
6
6
B
B
0
0
0
0
abs
abs