Datasheet

Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 180 of 1130
REJ09B0327-0400
7.1.2 Block Diagram
Figure 7.1 shows a block diagram of the DTC.
The DTC’s register information is stored in the on-chip RAM
*
. A 32-bit bus connects the DTC to
the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register
information.
Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.
Interrupt
request
Interrupt controller DTC
Internal address bus
DTC activation
request
Control logic
Register information
MRA MRB
CRA CRB
DAR SAR
CPU interrupt
request
On-chip
RAM
Internal data bus
Legend:
MRA, MRB: DTC mode registers A and B
CRA, CRB: DTC transfer count registers A and B
SAR: DTC source address register
DAR: DTC destination address register
DTCERA to DTCERE: DTC enable registers A to E
DTVECR: DTC vector register
DTCERA
to
DTCERE DTVECR
Figure 7.1 Block Diagram of DTC