Datasheet

Section 6 Bus Controller
Rev. 4.00 Sep 27, 2006 page 172 of 1130
REJ09B0327-0400
By program wait
T
1
Address bus
φ
AS/IOS (IOSE = 0)
RD
Data bus
Read data
Read
HWR, LWR
Write data
Write
Note: indicates the timing of WAIT pin sampling using the φ clock.
WAIT
Data bus
T
2
T
w
T
w
T
w
T
3
By WAIT pin
Figure 6.13 Example of Wait State Insertion Timing
The settings after a reset are: 3-state access, insertion of 3 program wait states, and WAIT input
disabled.