Datasheet

Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 136 of 1130
REJ09B0327-0400
Figure 5.7 shows a block diagram of the priority decision circuit.
ICR
UII
Default priority
determination
Vector
number
Interrupt
acceptance control
and 3-level mask
control
Interrupt
source
Interrupt control modes
0 and 1
Figure 5.7 Block Diagram of Interrupt Control Operation
Interrupt Acceptance Control and 3-Level Control
In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is
performed by means of the I and UI bits in CCR, and ICR (control level).
Table 5.6 shows the interrupts selected in each interrupt control mode.