Datasheet

Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 134 of 1130
REJ09B0327-0400
Address bus
Break request
signal
Breakpoint
NOP instruction is executed at breakpoint address H'0312 and
next address, H'0314; fetch from address H'0316 starts after
end of exception handling.
φ
Instruction
fetch
Internal
operation
Internal
operation
Vector
fetch
Stack save
Instruction
fetch
H'0310
NOP
execution
H'0310 NOP
H'0312 NOP
H'0314 NOP
H'0316 NOP
NOP
execution
NOP
execution
Interrupt exception handling
H'0312 H'0314 H'0316 H'0318 H'0036SP-2 SP-4
• Program area in on-chip memory, 1-state execution instruction at specified break address
Instruction
fetch
Address bus
Break request
signal
Breakpoint
MOV instruction is executed at breakpoint address H'0312,
NOP instruction at next address, H'0316, is not executed;
fetch from address H'0316 starts after end of exception handling.
φ
Internal
operation
Internal
operation
Vector
fetch
Stack save
Instruction
fetch
H'0310
NOP
execution
H'0310 NOP
H'0312 MOV.W #xx:16,Rd
H'0316 NOP
H'0318 NOP
MOV.W
execution
Interrupt exception handling
H'0312 H'0314 H'0316 H'0318 H'0036SP-2 SP-4
• Program area in on-chip memory, 2-state execution instruction at specified break address
Address bus
Break request
signal
Breakpoint
NOP instruction at breakpoint address H'0312 is not executed;
fetch from address H'0312 starts after end of exception handling.
φ
Instruction
fetch
Internal
operation
Internal
operation
Vector
fetch
Stack save
H'0310
NOP
execution
H'0310 NOP
H'0312 NOP
H'0314 NOP
H'0316 NOP
Interrupt exception handling
H'0312 H'0314 H'0036SP-2 SP-4
• Program area in external memory (2-state access, 16-bit-bus access),
1-state execution instruction at specified break address
Instruction
fetch
Instruction
fetch
Instruction
fetch
Instruction
fetch
Instruction
fetch
Instruction
fetch
Instruction
fetch
Instruction
fetch
Instruction
fetch
Instruction
fetch
Figure 5.6 Examples of Address Break Timing