Datasheet

Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 128 of 1130
REJ09B0327-0400
Interrupts KIN15 to KIN0
Interrupts KIN15 to KIN0 are requested by input signals at pins KIN15 to KIN 0. When any of
pins KIN15 to KIN0 are used as key-sense inputs, the corresponding KMIMR bits should be
cleared to 0 to enable those key-sense input interrupts. The remaining unused key-sense input
KMIMR bits should be set to 1 to disable those interrupts. Interrupts KIN15 to KIN8 correspond
to the IRQ7 interrupt, and interrupts KIN7 to KIN0 correspond to the IRQ6 interrupt. Interrupt
request generation pin conditions, interrupt request enabling, interrupt control level setting, and
interrupt request status indications, are all in accordance with the IRQ7 and IRQ6 interrupt
settings.
When pins KIN7 to KIN0 or KIN15 to KIN8 are used as key-sense interrupt input pins, either
low-level sensing or falling-edge sensing must be designated as the interrupt sense condition for
the corresponding interrupt source (IRQ6 or IRQ7).
5.3.2 Internal Interrupts
There are 43 sources for internal interrupts from on-chip supporting modules, plus one software
interrupt source (address break).
• For each on-chip supporting module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. If any one of these is set to
1, an interrupt request is issued to the interrupt controller.
• The interrupt control level can be set by means of ICR.
• The DTC can be activated by an FRT, TMR, SCI, or other interrupt request. When the DTC is
activated by an interrupt, the interrupt control mode and interrupt mask bits have no effect.
5.3.3 Interrupt Exception Vector Table
Table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority.
Priorities among modules can be set by means of ICR. The situation when two or more modules
are set to the same priority, and priorities within a module, are fixed as shown in table 5.4.