Datasheet

Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 117 of 1130
REJ09B0327-0400
5.2 Register Descriptions
5.2.1 System Control Register (SYSCR)
7
CS2E
0
R/W
6
IOSE
0
R/W
5
INTM1
0
R
4
INTM0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
HIE
0
R/W
Bit
Initial value
Read/Write
SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the
detected edge for NMI, among other functions.
Only bits 5, 4, and 2 are described here; for details on the other bits, see section 3.2.2, System
Control Register (SYSCR).
SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of four
interrupt control modes for the interrupt controller. The INTM1 bit must not be set to 1.
Bit 5 Bit 4
Interrupt
INTM1 INTM0 Control Mode Description
0 0 0 Interrupts are controlled by I bit (Initial value)
1 1 Interrupts are controlled by I and UI bits and ICR
1 0 2 Cannot be used in this LSI
1 3 Cannot be used in this LSI
Bit 2—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.
Bit 2
NMIEG Description
0 Interrupt request generated at falling edge of NMI input (Initial value)
1 Interrupt request generated at rising edge of NMI input