Datasheet

Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 87 of 1130
REJ09B0327-0400
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0
RAME Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled (Initial value)
3.2.3 Bus Control Register (BCR)
7
ICIS1
1
R/W
6
ICIS0
1
R/W
5
BRSTRM
0
R/W
4
BRSTS1
1
R/W
3
BRSTS0
0
R/W
0
IOS0
1
R/W
2
—
1
R/W
1
IOS1
1
R/W
Bit
Initial value
Read/Write
BCR is an 8-bit readable/writable register that specifies the external memory space access mode,
and the I/O area range when the AS pin is designated for use as the I/O strobe. For details on bits 7
to 2, see section 6.2.1, Bus Control Register (BCR).
BCR is initialized to H'D7 by a reset and in hardware standby mode.
Bits 1 and 0—IOS Select 1 and 0 (IOS1, IOS0): These bits specify the addresses for which the
AS/IOS pin output goes low when IOSE = 1.
BCR
Bit 1 Bit 0
IOS1 IOS0 Description
0 0 The AS/IOS pin output goes low in accesses to addresses
H'(FF)F000 to H'(FF)F03F
1 The AS/IOS pin output goes low in accesses to addresses
H'(FF)F000 to H'(FF)F0FF
1 0 The AS/IOS pin output goes low in accesses to addresses
H'(FF)F000 to H'(FF)F3FF
1 The AS/IOS pin output goes low in accesses to addresses
H'(FF)F000 to H'(FF)FE4F
*
(Initial value)
Note: * In the H8S/2148 F-ZTAT A-mask version and H8S/2147 F-ZTAT A-mask version, the
address range is from H'(FF)F000 to H'(FF)F7FF.