Datasheet

Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
Rev. 4.00 Sep 27, 2006 page 1126 of 1130
REJ09B0327-0400
Appendix E Timing of Transition to and Recovery from
Hardware Standby Mode
E.1 Timing of Transition to Hardware Standby Mode
(1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10
system clock cycles before the STBY signal goes low, as shown in figure E.1. RES must
remain low until STBY signal goes low (minimum delay from STBY low to RES high: 0 ns).
STBY
RES
t
2
≥ 0 nst
1
≥ 10 t
cyc
Figure E.1 Timing of Transition to Hardware Standby Mode
(2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do
not need to be retained, RES does not have to be driven low as in (1).
E.2 Timing of Recovery from Hardware Standby Mode
Drive the RES signal low at least 100 ns before STBY goes high to execute a reset.
STBY
RES
t
OSC1
t ≥ 100 ns
Figure E.2 Timing of Recovery from Hardware Standby Mode