Datasheet

Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1108 of 1130
REJ09B0327-0400
D
R
QD
P81DR
C
Reset
R
Q
P81DDR
C
Reset
WP8D
Mode 2, 3
Hardware standby
EXPE
CS2E
HI12E
WP8
HIF
CS2 input
HIF
GA20 output
Output enable
P81
RP8
WP8D: Write to P8DDR
WP8: Write to port 8
RP8: Read port 8
Internal data bus
Legend:
Figure C.24 Port 8 Block Diagram (Pin P81)