Datasheet

Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1093 of 1130
REJ09B0327-0400
D
R
QD
P42DR
C
Reset
R
Q
P42DDR
C
Reset
WP4D
*
1
*
2
WP4
SCI2
Input enable
Clock output
SDA1 output
SDA1 input
Transmit enable
Output enable
Clock output
IIC1
8-bit timer 0
Reset input
P42
Hardware standby
RP4
WP4D: Write to P4DDR
WP4: Write to port 4
RP4: Read port 4
Notes: 1. Output enable signal
2. Open drain control signal
Internal data bus
Legend:
Figure C.8 Port 4 Block Diagram (Pin P42)