Datasheet

Appendix C I/O Port Block Diagrams
Rev. 4.00 Sep 27, 2006 page 1086 of 1130
REJ09B0327-0400
Appendix C I/O Port Block Diagrams
C.1 Port 1 Block Diagram
R
QD
D
P1nPCR
C
Reset
R
QD
P1nDR
C
Reset
WP1P
R
Q
P1nDDR
C
Reset
WP1D
WP1
Internal data bus
Internal address bus
8-bit PWM
PWM output enable
PWM output
P1n
*
RP1P
RP1
Mode 2, 3
Mode 1
Hardware
standby
Mode 1
EXPE
WP1P: Write to P1PCR
WP1D: Write to P1DDR
WP1: Write to port 1
RP1P: Read P1PCR
RP1: Read port 1
Notes: n = 0 to 7
* Set priority
Legend:
Figure C.1 Port 1 Block Diagram