Datasheet

Section 2 CPU

Rev. 4.00 Sep 27, 2006 page 66 of 1130

REJ09B0327-0400

absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and

BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.

Table 2.4 Addressing Modes

No. Addressing Mode Symbol

1 Register direct Rn

2 Register indirect @ERn

3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn)

4 Register indirect with post-increment

@ERn+

@–ERn

5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32

6 Immediate #xx:8/#xx:16/#xx:32

7 Program-counter relative @(d:8,PC)/@(d:16,PC)

8 Memory indirect @@aa:8

The register field of the instruction code specifies an 8-, 16-, or 32-bit general register containing

the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to

E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.

The register field of the instruction code specifies an address register (ERn) which contains the

address of the operand in memory. If the address is a program instruction address, the lower 24

bits are valid and the upper 8 bits are all assumed to be 0 (H'00).

A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn)

specified by the register field of the instruction, and the sum gives the address of a memory

operand. A 16-bit displacement is sign-extended when added.