Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1061 of 1130
REJ09B0327-0400
BCR—Bus Control Register H'FFC6 Bus Controller
7
ICIS1
1
R/W
6
ICIS0
1
R/W
5
BRSTRM
0
R/W
4
BRSTS1
1
R/W
3
BRSTS0
0
R/W
0
IOS0
1
R/W
2
—
1
R/W
1
IOS1
1
R/W
Bit
Initial value
Read/Write
IOS select
IOS1
Address for which AS/IOS pin
output goes low when IOSE = 1
0 Low in access to address
H'(FF)F000 to H'(FF)F03F
IOS0
0
Low in access to address
H'(FF)F000 to H'(FF)F0FF
1
1 Low in access to address
H'(FF)F000 to H'(FF)F3FF
0
Low in access to address
H'(FF)F000 to H'(FF)FE4F
1
Burst cycle select 0
0 Max. 4 words in burst access
1 Max. 8 words in burst access
Burst cycle select 1
0 Burst cycle comprises 1 state
1 Burst cycle comprises 2 states
Burst ROM enable
0 Basic bus interface
1 Burst ROM interface
Idle cycle insert 0
0 Idle cycle not inserted in case of successive
external read and external write cycles
1 Idle cycle inserted in case of successive
external read and external write cycles
Reserved bit