Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1059 of 1130
REJ09B0327-0400
SYSCR—System Control Register H'FFC4 System
7
CS2E
0
R/W
6
IOSE
0
R/W
5
INTM1
0
R
4
INTM0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
HIE
0
R/W
Bit
Initial value
Read/Write
RAM Enable
0
On-chip RAM is disabled
1 On-chip RAM is enabled
Host interface enable
0
Addresses H'(FF)FFF0 to H'(FF)FFF7
and H'(FF)FFFC to H'(FF)FFFF are
used for access to 8-bit timer (channel
X and Y) data registers and control
registers, and timer connection
control registers
1 Addresses H'(FF)FFF0 to H'(FF)FFF7
and H'(FF)FFFC to H'(FF)FFFF are
used for access to host interface data
registers and control registers, and
keyboard controller and MOS input
pull-up control registers
NMI edge select
0
Falling edge
1 Rising edge
External reset
0
Reset generated by watchdog timer overflow
1 Reset generated by an external reset
Interrupt control mode select
INTM1
Interrupt control mode 0
Interrupt control mode 1
INTM0 Description
00
1
CS2 enable
0
CS2 pin function halted
(CS2 fixed high internally)
0
CS2E FGA20E
1
1 CS2 pin function selected for P81/CS2 pin0
CS2 pin function selected for P90/ECS2 pin1
Description
SYSCR
Bit 7
HICR
Bit 0
IOS enable
Note: * In the H8S/2148 F-ZTAT A-mask version and H8S/2147 F-ZTAT A-mask version,
the address range is from H'(FF)F000 to H'(FF)F7FF.
0
The AS/IOS pin functions as the address strobe pin
(Low output when accessing an external area)
1 The AS/IOS pin functions as the I/O strobe pin
(Low output when accessing a specified address from H'(FF)F000 to H'(FF)FE4F)
*