Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1055 of 1130
REJ09B0327-0400
P8DDR—Port 8 Data Direction Register H'FFBD (W) Port 8
7
—
1
—
6
P86DDR
0
W
5
P85DDR
0
W
4
P84DDR
0
W
3
P83DDR
0
W
0
P80DDR
0
W
2
P82DDR
0
W
1
P81DDR
0
W
Bit
Initial value
Read/Write
Specification of input or output for port 8 pins
PBPIN—Port B Input Data Register H'FFBD (R) Port B
7
PB7PIN
—*
R
6
PB6PIN
—*
R
5
PB5PIN
—*
R
4
PB4PIN
—*
R
3
PB3PIN
—*
R
0
PB0PIN
—*
R
2
PB2PIN
—*
R
1
PB1PIN
—*
R
Bit
Initial value
Read/Write
Note: * Determined by state of pins PB7 to PB0.
Port B pin states
PBDDR—Port B Data Direction Register H'FFBE (W) Port B
7
PB7DDR
0
W
6
PB6DDR
0
W
5
PB5DDR
0
W
4
PB4DDR
0
W
3
PB3DDR
0
W
0
PB0DDR
0
W
2
PB2DDR
0
W
1
PB1DDR
0
W
Bit
Initial value
Read/Write
Specification of input or output for port B pins
P7PIN—Port 7 Input Data Register H'FFBE (R) Port 7
7
P77PIN
—*
R
6
P76PIN
—*
R
5
P75PIN
—*
R
4
P74PIN
—*
R
3
P73PIN
—*
R
0
P70PIN
—*
R
2
P72PIN
—*
R
1
P71PIN
—*
R
Bit
Initial value
Read/Write
Note: * Determined by state of pins P77 to P70.
Port 7 pin states