Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1033 of 1130
REJ09B0327-0400
SCR1—Serial Control Register 1 H'FF8A SCI1
SCR2—Serial Control Register 2 H'FFA2 SCI2
SCR0—Serial Control Register 0 H'FFDA SCI0
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
0
CKE0
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
Bit
Initial value
Read/Write
Clock enable 1 and 0
0
Asynchronous
mode
Synchronous
mode
0
Asynchronous
mode
1
Synchronous
mode
1 Asynchronous
mode
0
Synchronous
mode
Asynchronous
mode
1
Synchronous
mode
Internal clock/SCK pin
functions as I/O port
Internal clock/SCK pin
functions as serial clock output
Internal clock/SCK pin
functions as clock output
Internal clock/SCK pin
functions as serial clock output
External clock/SCK pin
functions as clock input
External clock/SCK pin
functions as serial clock input
External clock/SCK pin
functions as clock input
External clock/SCK pin
functions as serial clock input
Transmit end interrupt enable
0
Transmit-end interrupt (TEI) request disabled
1 Transmit-end interrupt (TEI) request enabled
Multiprocessor interrupt enable
0
Multiprocessor interrupts disabled (normal reception mode)
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When data with MPB = 1 is received
1 Multiprocessor interrupts enabled
Receive interrupt (RXI) requests, receive-error interrupt (ERI)
requests, and setting of the RDRF, FER, and ORER flags in
SSR are disabled until data with the multiprocessor bit set to
1 is received
Receive enable
0
Reception disabled
1 Reception enabled
Transmit enable
0
Transmission disabled
1 Transmission enabled
Receive interrupt enable
0
Receive-data-full interrupt (RXI)
request and receive-error interrupt
(ERI) request disabled
1 Receive-data-full interrupt (RXI)
request and receive-error interrupt
(ERI) request enabled
Transmit interrupt enable
0
Transmit-data-empty interrupt
(TXI) request disabled
1 Transmit-data-empty interrupt
(TXI) request enabled