Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1018 of 1130
REJ09B0327-0400
DTCER—DTC Enable Register H'FEEE to H'FEF2 DTC
7
DTCE7
0
R/W
6
DTCE6
0
R/W
5
DTCE5
0
R/W
4
DTCE4
0
R/W
3
DTCE3
0
R/W
0
DTCE0
0
R/W
2
DTCE2
0
R/W
1
DTCE1
0
R/W
Bit
Initial value
Read/Write
DTC activation enable
0 DTC activation by interrupt is disabled
[Clearing conditions]
• When data transfer ends with the DISEL bit set to 1
• When the specified number of transfers end
1 DTC activation by interrupt is enabled
[Holding condition]
When the DISEL bit is 0 and the specified number of transfers
have not ended
DTVECR—DTC Vector Register H'FEF3 DTC
7
SWDTE
0
R/(W)
*
6
DTVEC6
0
R/W
5
DTVEC5
0
R/W
4
DTVEC4
0
R/W
3
DTVEC3
0
R/W
0
DTVEC0
0
R/W
2
DTVEC2
0
R/W
1
DTVEC1
0
R/W
Bit
Initial value
Read/Write
Note: *
Sets vector number for DTC software activation
DTC software activation enable
0 DTC software activation is disabled
[Clearing condition]
When the DISEL bit is 0 and the specified number of transfers have
not ended
1 DTC software activation is enabled
[Holding conditions]
• When data transfer ends with the DISEL bit set to 1
• When the specified number of transfers end
• During software-activated deta transfer
A value of 1 can always be written to the SWDTE bit, but 0 can only be written
after 1 is read.