Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1008 of 1130
REJ09B0327-0400
IDR3—Input Data Register 3 H'FE84 HIF
IDR4—Input Data Register 4 H'FE8C HIF
7
IDR7
—
R
W
6
IDR6
—
R
W
5
IDR5
—
R
W
4
IDR4
—
R
W
3
IDR3
—
R
W
0
IDR0
—
R
W
2
IDR2
—
R
W
1
IDR1
—
R
W
Bit
Initial value
Slave R/W
Host R/W
Stores host data bus contents at rise of IOW when CS is low
ODR3—Output Data Register 3 H'FE85 HIF
ODR4—Output Data Register 4 H'FE8D HIF
7
ODR7
—
R/W
R
6
ODR6
—
R/W
R
5
ODR5
—
R/W
R
4
ODR4
—
R/W
R
3
ODR3
—
R/W
R
0
ODR0
—
R/W
R
2
ODR2
—
R/W
R
1
ODR1
—
R/W
R
Bit
Initial value
Slave R/W
Host R/W
ODR contents are output to the host data bus
when HA0 is low, CS is low, and IOR is low