Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1005 of 1130
REJ09B0327-0400
MRA—DTC Mode Register A H'EC00–H'EFFF DTC
7
SM1
Undefined
—
6
SM0
Undefined
—
5
DM1
Undefined
—
4
DM0
Undefined
—
3
MD1
Undefined
—
0
Sz
Undefined
—
2
MD0
Undefined
—
1
DTS
Undefined
—
Bit
Initial value
Read/Write
DTC data transfer size
0 Byte-size transfer
1 Word-size transfer
DTC transfer mode select
0 Destination side is repeat
area or block area
1 Source side is repeat area
or block area
DTC mode
0 Normal mode
Repeat mode
0
1
1 Block transfer mode0
—1
Destination address mode
0 DAR is fixed
DAR is incremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
—
0
1
DAR is decremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
1
Source address mode
0 SAR is fixed
SAR is incremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
—
0
1
SAR is decremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
1