Datasheet
Appendix A Instruction Set
Rev. 4.00 Sep 27, 2006 page 956 of 1130
REJ09B0327-0400
XORC #xx:8,CCR
XORC #xx:8,EXR
Mnemonic
Size
Instruction Format
1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Instruc-
tion
XORC B
B
0
0
5
1
4
1 0 5
IMM
IMM
Notes: Bit 7 of the 4th byte of the MOV.L ERs, @ (d:32, ERd) instruction can be either 0 or 1.
Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Only registers ER0 to ER6 should be used when using the STM/LDM instruction.
Legend:
Address Registers
32-Bit Registers
Register
Field
General
Register
Register
Field
General
Register
Register
Field
General
Register
000
001
•
•
•
111
ER0
ER1
•
•
•
ER7
0000
0001
•
•
•
0111
1000
1001
•
•
•
1111
R0
R1
•
•
•
R7
E0
E1
•
•
•
E7
0000
0001
•
•
•
0111
1000
1001
•
•
•
1111
R0H
R1H
•
•
•
R7H
R0L
R1L
•
•
•
R7L
16-Bit Register 8-Bit Register
IMM:
abs:
disp:
rs, rd, rn:
ers, erd, ern, erm:
Immediate data (2, 3, 8, 16, or 32 bits)
Absolute address (8, 16, 24, or 32 bits)
Displacement (8, 16, or 32 bits)
Register field (4 bits, indicating an 8-bit or 16-bit register. rs, rd, and rn correspond to operand formats Rs, Rd, and Rn, respectively.)
Register field (3 bits, indicating an address register or 32-bit register. ers, erd, ern, and erm correspond to operand formats ERs, ERd,
ERn, and ERm, respectively.)
1.
2.
3.
The correspondence between register fields and general registers is shown in the following table.