Datasheet

Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 562 of 1130
REJ09B0327-0400
17.1.3 Input/Output Pins
Table 17.1 lists the input/output pins used by the keyboard buffer controller.
Table 17.1 Keyboard Buffer Controller Input/Output Pins
Channel Name Abbreviation
*
I/O Function
0 KBC clock I/O pin (KCLK0) PS2AC I/O KBC clock input/output
KBC data I/O pin (KD0) PS2AD I/O KBC data input/output
1 KBC clock I/O pin (KCLK1) PS2BC I/O KBC clock input/output
KBC data I/O pin (KD1) PS2BD I/O KBC data input/output
2 KBC clock I/O pin (KCLK2) PS2CC I/O KBC clock input/output
KBC data I/O pin (KD2) PS2CD I/O KBC data input/output
Note: * These are the external I/O pin names. In the text, clock I/O pins are referred to as KCLK
and data I/O pins as KD, omitting the channel designations.
17.1.4 Register Configuration
Table 17.2 lists the registers of the keyboard buffer controller.
Table 17.2 Keyboard Buffer Controller Registers
Channel Name Abbreviation R/W Initial Value Address
*
1
0 Keyboard control register H KBCRH0 R/(W)
*
2
H'70 H'FED8
Keyboard control register L KBCRL0 R/W H'70 H'FED9
Keyboard data buffer register KBBR0 R H'00 H'FEDA
1 Keyboard control register H KBCRH1 R/(W)
*
2
H'70 H'FEDC
Keyboard control register L KBCRL1 R/W H'70 H'FEDD
Keyboard data buffer register KBBR1 R H'00 H'FEDE
2 Keyboard control register H KBCRH2 R/(W)
*
2
H'70 H'FEE0
Keyboard control register L KBCRL2 R/W H'70 H'FEE1
Keyboard data buffer register KBBR2 R H'00 H'FEE2
Common Module stop control register MSTPCRH R/W H'3F H'FF86
MSTPCRL R/W H'FF H'FF87
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written in bits 2 and 1, to clear the flags.