Datasheet

Section 16 I
2
C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 552 of 1130
REJ09B0327-0400
• Notes on TRS Bit Setting in Slave Mode
From the detection of the rising edge of the 9th clock cycle or of a stop condition to when the
rising edge of the next SCL pin signal is detected (the period indicated as (a) in figure 16.23)
in the slave mode of the I
2
C bus interface, the value set in the TRS bit in the ICCR register is
effective immediately.
However, at other times (indicated as (b) in figure 16.23) the value set in the TRS bit is put on
hold until the next rising edge of the 9th clock cycle or stop condition is detected, rather than
taking effect immediately.
This results in the actual internal value of the TRS bit remaining 1 (transmit mode) and no
acknowledge bit being sent at the 9th clock cycle address receive completion in the case of an
address receive operation following a restart condition input with no stop condition
intervening.
When receiving an address in the slave mode, clear the TRS bit to 0 during the period
indicated as (a) in figure 16.23.
To cancel the holding of the SCL bit low by the wait function in the slave mode, clear the TRS
bit to 0 and then perform a dummy read of the ICDR register.
SDA
SCL
A
(a) TRS bit
Detection of rise of 9th
transmit/receive clock
Address reception
Data
transmission
89
123456789
(a) (b)
TRS bit setting value
TRS bit effective value
Period in which TRS bit setting is retained
Resumption condition
(b) TRS bit
Detection of rise of 9th
transmit/receive clock
Figure 16.23 TRS Bit Setting Timing in Slave Mode