Datasheet

Section 16 I
2
C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 517 of 1130
REJ09B0327-0400
Bit 7—I
2
C Extra Buffer Select (IICS): Designates bits 7 to 4 of port A as the same kind of
output buffer as SCL and SDA. This bit is used when implementing the I
2
C interface by software
only.
Bit 7
IICS Description
0 PA7 to PA4 are normal I/O pins (Initial value)
1 PA7 to PA4 are I/O pins with bus driving capability
Bits 6 and 5—I
2
C Transfer Select 1 and 0 (IICX1 and 0): This bit, together with bits CKS2 to
CKS0 in ICMR, selects the transfer rate in master mode. For details, see section 16.2.4, I
2
C Bus
Mode Register (ICMR).
Bit 4—I
2
C Master Enable (IICE): Controls CPU access to the I
2
C bus interface data and control
registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR).
Bit 4
IICE Description
0 CPU access to I
2
C bus interface data and control registers is disabled (Initial value)
1 CPU access to I
2
C bus interface data and control registers is enabled
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers, the power-down mode control registers, and the supporting module
control registers. See section 3.2.4, Serial Timer Control Register (STCR), for details.
Bit 2—Reserved: Do not write 1 to this bit.
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICSK0): These bits, together with
bits CKS2 to CKS0 in TCR, select the clock input to the timer counters (TCNT). For details, see
section 12.2.4, Timer Control Register (TCR).