Datasheet

Section 16 I
2
C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 504 of 1130
REJ09B0327-0400
Bit 2 Bit 1 Bit 0 Bits/Frame
BC2 BC1 BC0 Synchronous Serial Format I
2
C Bus Format
0 0 0 8 9 (Initial value)
11 2
10 2 3
13 4
100 4 5
15 6
10 6 7
17 8
16.2.5 I
2
C Bus Control Register (ICCR)
Bit
Initial value
Read/Write
Note: * Only 0 can be written, to clear the flag.
7
ICE
0
R/W
6
IEIC
0
R/W
5
MST
0
R/W
4
TRS
0
R/W
3
ACKE
0
R/W
0
SCP
1
W
2
BBSY
0
R/W
1
IRIC
0
R/(W)
*
ICCR is an 8-bit readable/writable register that enables or disables the I
2
C bus interface, enables or
disables interrupts, selects master or slave mode and transmission or reception, enables or disables
acknowledgement, confirms the I
2
C bus interface bus status, issues start/stop conditions, and
performs interrupt flag confirmation.
ICCR is initialized to H'01 by a reset and in hardware standby mode.
Bit 7—I
2
C Bus Interface Enable (ICE): Selects whether or not the I
2
C bus interface is to be
used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer
operations are enabled. When ICE is cleared to 0, the I
2
C bus interface module is halted and its
internal states are cleared.
The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers can
be accessed when ICE is 1.