Datasheet

Section 11 16-Bit Free-Running Timer

Rev. 4.00 Sep 27, 2006 page 320 of 1130

REJ09B0327-0400

Bit 7

IEDGA Description

0 Capture on the falling edge of FTIA (Initial value)

1 Capture on the rising edge of FTIA

Bit 6—Input Edge Select B (IEDGB): Selects the rising or falling edge of the input capture B

signal (FTIB).

Bit 6

IEDGB Description

0 Capture on the falling edge of FTIB (Initial value)

1 Capture on the rising edge of FTIB

Bit 5—Input Edge Select C (IEDGC): Selects the rising or falling edge of the input capture C

signal (FTIC).

Bit 5

IEDGC Description

0 Capture on the falling edge of FTIC (Initial value)

1 Capture on the rising edge of FTIC

Bit 4—Input Edge Select D (IEDGD): Selects the rising or falling edge of the input capture D

signal (FTID).

Bit 4

IEDGD Description

0 Capture on the falling edge of FTID (Initial value)

1 Capture on the rising edge of FTID

Bit 3—Buffer Enable A (BUFEA): Selects whether ICRC is to be used as a buffer register for