Datasheet

Section 11 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 315 of 1130
REJ09B0327-0400
Bit 7
ICIAE Description
0 Input capture interrupt request A (ICIA) is disabled (Initial value)
1 Input capture interrupt request A (ICIA) is enabled
Bit 6—Input Capture Interrupt B Enable (ICIBE): Selects whether to request input capture
interrupt B (ICIB) when input capture flag B (ICFB) in TCSR is set to 1.
Bit 6
ICIBE Description
0 Input capture interrupt request B (ICIB) is disabled (Initial value)
1 Input capture interrupt request B (ICIB) is enabled
Bit 5—Input Capture Interrupt C Enable (ICICE): Selects whether to request input capture
interrupt C (ICIC) when input capture flag C (ICFC) in TCSR is set to 1.
Bit 5
ICICE Description
0 Input capture interrupt request C (ICIC) is disabled (Initial value)
1 Input capture interrupt request C (ICIC) is enabled
Bit 4—Input Capture Interrupt D Enable (ICIDE): Selects whether to request input capture
interrupt D (ICID) when input capture flag D (ICFD) in TCSR is set to 1.
Bit 4
ICIDE Description
0 Input capture interrupt request D (ICID) is disabled (Initial value)
1 Input capture interrupt request D (ICID) is enabled
Bit 3—Output Compare Interrupt A Enable (OCIAE): Selects whether to request output
compare interrupt A (OCIA) when output compare flag A (OCFA) in TCSR is set to 1.
Bit 3
OCIAE Description
0 Output compare interrupt request A (OCIA) is disabled (Initial value)
1 Output compare interrupt request A (OCIA) is enabled