Datasheet

Section 10 14-Bit PWM Timer (PWMX)
Rev. 4.00 Sep 27, 2006 page 305 of 1130
REJ09B0327-0400
2. OS = 1 (DADR corresponds to T
H
)
a. CFS = 0 [base cycle = resolution (T) ×
××
× 64]
t
H1
t
H2
t
H3
t
H255
t
H256
t
f1
t
f2
t
f255
t
f256
1 conversion cycle
t
f1
= t
f2
= t
f3
= · · · = t
f255
= t
f256
= T × 64
t
H1
+ t
H2
+ t
H3
+ · · · + t
H255
+ t
H256
= T
H
Figure 10.4 (3) Output Waveform
b. CFS = 1 [base cycle = resolution (T) ×
××
× 256]
t
H1
t
H2
t
H3
t
H63
t
H64
t
f1
t
f2
t
f63
t
f64
1 conversion cycle
t
f1
= t
f2
= t
f3
= · · · = t
f63
= t
f64
= T × 256
t
H1
+ t
H2
+ t
H3
+ · · · + t
H63
+ t
H64
= T
H
Figure 10.4 (4) Output Waveform